The present invention relates to a data processing apparatus and, more particularly, to a technique which can be suitably used for an MCU system requiring both high-speed operation and functional safety.
In some cases, an MCU (Micro Controller Unit) system is requested to satisfy both high-speed operation and functional safety. For example, in the field of automobile application, to realize automatic driving in an Advanced Driver Assistance System (ADAS), a determination MCU (brain chip) is used. The determination MCU is requested to satisfy both high-speed operation realizing extremely high-speed process and functional safety which guarantees safety in the whole system even in the case where a circuit operates due to a soft error or the like.
Such an MCU system is configured by combining a CPU (Central Processing Unit) capable of performing high-speed operation exceeding 1 GHz and a high-speed memory such as a TCM (Tightly Coupled Memory) which is tightly coupled to the CPU or a cache memory. For functional safety, a mechanism of detecting, in the case where a soft error occurs in the high-speed memory, occurrence of an error in the data which seems to be caused by the soft error, and correcting the error can be mounted.
Patent literature 1 discloses a cache memory device having a soft error correcting method which exerts a small influence on the performance of a processor performing a pipeline process. A parity bit and an error correction code (ECC) are added at the time of writing data into a data array, and a parity check is made at the time of reading. When a data error is detected, the pipeline is stalled, and an error correction is executed during the stall. Patent literature 2 discloses a method of correcting an error in a register file. The method has an error detecting step and an error correcting step. When an error is detected in the error detecting step, arithmetic processing is interrupted and the error correcting step is executed. Patent literature 3 discloses a single error detecting/correcting method, and patent literature 4 discloses an error correcting apparatus. In the case where a parity error is detected, error correction is made. Patent literature 5 discloses an error correcting circuit of a single error correction/double error detection method (SEC-DED) capable of correcting an error of even a large word size. Non-patent literature 1 describes a generator matrix and a check matrix of SEC-DEC intended to suppress circuit scale while assuring error correcting/detecting performance.